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(R)
MT8924
PCM Conference Circuit (PCC) Preliminary Information
Features
* * Supports up to 10 independent conferences for up to 32 PCM Voice Channels ST-BUS compatible 2.048 Mb/s PCM Serial Interface (also supports 1.536 Mb/s and 1.544 Mb/s data rates) Per channel digital gain control (0/-3/-6 dB) Parallel microprocessor port for device control Programmable noise suppression External Tone Input Pin selectable A/-Law format Low power CMOS technology Available in 24 Pin PDIP and SOIC packages
ISSUE 1
April 1994
Ordering Information MT8924AE 24 Pin Plastic DIP MT8924AS 24 Pin SOIC 0 C to +70 C
Description
The MT8924 is designed to provide conference call capability in digital switching systems. It allows up to 10 independent conferences to be set for up to 32 PCM voice channels. A/-Law companded data from the PCM input port is converted to linear format, processed by a dedicated arithmetic unit, re-converted to companded format and then sent to the PCM output port.The PCM output signal contains all the information of each channel connected in conference except its own. Programmable attenuation and noise suppression are provided for channels connected in conference or transparent mode. Additionally, an input for an external tone is featured that can be used as a signal to indicate to connected parties that they are on a conference call.
OS
* * * * * * *
Applications
* * * Digital PBX / KTS Conference bridges Digital C.O. switches
Overflow Attenuation/Noise Suppression /A-Law to Linear Channel RAM and Adder
Linear to /A-Law
MUX
DSTi
Serial-to-Parallel Conversion
Parallel-to-Serial Conversion
DSTo
PCM Mode Control
Timebase
PCM Tone Generator
Control
RESET
A/
Cki
F0i
Cko
TF
TD
RD
WR
D0-D7
CS
C/D
Figure 1 - Functional Block Diagram
8-3
MT8924
Preliminary Information
TD TF RESET OS DSTo D7 D6 D5 D4 D3 D2 D1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VSS A/ DSTi Cko Cki F0i WR RD CS C/D VDD D0
Figure 2 - Pin Connections
Pin Description
Pin # 1 Name TD Description Tone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all channels have the same tone during the same frame number. When TD is Low, normal operation is enabled. Tone Frequency (Input). This input is connected to an external squarewave generator. TF is strobed by frame pulse F0i so that all channels have the same tone frequency during the same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale value, and is activated when TD is High. Master RESET (Input). This input is used for system initialization after power up, or when the companding law format has been changed. The RESET pin is strobed by the rising edge of clock Cki. Complete circuit initialization takes two frame periods. Initialization disables the output drivers of the microprocessor interface and DSTo. Overflow Signalling (Output). When OS is Low, a conference is in the overflow condition. This signal is delayed by half of a timeslot relative to the beginning of the output channel of the conference in overflow (see Figure 9). ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is 2.048 Mb/s.
2
TF
3
RESET
4
OS
5
DSTo
6-13
D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are transferred to and from the microprocessor (where D0 is the least significant bit). The bus is in a high impedance state when RESET is Low and/or CS is High. VDD C/D Positive Supply Voltage. Nominally 5 volts. Control/Data Select (Input). The signal on this input defines whether the information on the data bus should be interpreted as opcode or data. During a write operation a Low signal defines the bus content as data, while a High signal defines it as opcode. During a read operation this input differentiates overflow status between the first eight channels for C/D being LOW, and the last two channels for C/D being HIGH (see Instruction 4). This input also allows status monitoring (see Instruction 6) during a read operation. Chip Select (Input). This active low input selects the device for microprocessor read/write operations. When CS is Low, data and instructions can be transferred to or from the microprocessor, and when CS is High, the data bus is in a high impedance state. Read (Input). This active low input is for the read signal on the microprocessor interface. The data bus is updated on the falling edge of RD. Write Input. This active low input is for the write signal on the microprocessor interface. The data bus is strobed on the rising edge of WR.
14 15
16
CS
17 18
RD WR
8-4
Preliminary Information
Pin Description (continued)
Pin # 19 Name F0i Description
MT8924
Frame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i determines the start of a new frame and must correspond to the first bit of the first channel. When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the Extra (193rd) bit. Clock (Input). This signal is the timing reference used for all internal operations. The PCM bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable clock frequency is 4096 kHz. Clock (Output). This pin provides the master clock for a digital crosspoint switch (e.g., MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924 to operate in 1544 kbit/s systems. ST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating mode is selected, the first bit of the first channel defines the extra bit. A/ - Law Select Input. When A/ is High, A-Law is selected, and when A/ is Low, -Law is selected. The companding law selection must be done before initializing the device using the RESET pin. Negative Power Supply Voltage. Nominally 0 Volts.
20
Cki
21
Cko
22
DSTi
23
A/
24
VSS
Functional Description
The MT8924 is a device designed to provide conferencing in a digital switching system in any combination for up to all 32 channels of a 2048 kbit/s ST-BUS stream (see Figure 3). The information of channel N, frame M is first converted to Linear PCM and then added to the signal from other conferencees during the first half of
channel N+1, frame M and subtracted during the second half of channel N-1, frame M+1. After Linearto-PCM conversion the subtraction result goes to the parallel-to-serial converter, and appears at the output on the N+1 channel, M+1 frame with respect to the corresponding sending party information (see Figure 4). To a microprocessor the MT8924 appears as a memory mapped peripheral device that can be controlled by a set of six instructions. These commands can be used to establish or cancel conferences between the PCM channels and also to transmit control messages on specific operating modes. The microprocessor can initiate and receive status messages or check conference connections that are currently in operation.
Microcontroller
STi0 . . . . STix-1 STix
MT8980/81/82 Digital Switch
STo0 . . . . STox-1 STox
Input Information
A B C
Output Information
B+C A+C A+B
DSTi
N N+1 N+2
MT8924
N+1 N+2 N+3
DSTo
MT8924 PCM Conference Circuit (PCC)
Input Channels Frame M
Output Channels Frame M+1
Figure 3 -Typical Conference Connection
Figure 4 - Input/Output Channel Relationship
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MT8924
PCM Byte +ve input B7 - B0 A-Law 1/4096 9/4096 16/4096 32/4096 -Law 1/8159 9/8159 16/8159 32/8159 1000 0000 1000 0100 1000 1000 1000 1111 1111 1111 1111 1011 1111 0111 1111 0000
Preliminary Information
Noise Threshold
-ve input B7 - B0 0000 0000 0000 0100 0000 1000 0000 1111 0111 1111 0111 1011 0111 0111 0111 0000
Table 1 - PCM Noise Suppression Threshold Levels Overflow Detection / Input Channel Attenuation If the sum of the channels involved in one conference exceeds the full scale value of the accumulator, an overflow condition is generated which can be monitored specifically by reading the status of the overflow register. If an overflow condition occurs, then each channel in a conference can be independently attenuated if desired. Alternatively, a conference in the overflow condition can be detected using the OS signal in conjunction with frame pulse F0i. OS will be low during the second half of a general output channel slot time N, if channel N belongs to a conference in overflow (see Figure 11). This information can be used to control input channel attenuation through software control.
F1 0
F0 0 + Full Scale + 0 Level - 0 Level - Full Scale + Full Scale + 0 Level - 0 Level - Full Scale + Full Scale + 0 Level - 0 Level - Full Scale + Full Scale + 0 Level - 0 Level - Full Scale
B7 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
B6 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
B5 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
B4 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
B3 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
B2 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
B1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
B0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
Comments No Inversion
0
1
Even Bit Inversion
1
0
Odd Bit Inversion
1
1
Bit Inversion
Table 2 - PCM Byte Format
B7 (sign bit) is the MSB and B0 is the LSB F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5
8-6
Preliminary Information
Noise Suppression When noise suppression is enabled for a specific input channel then the PCM bytes for this channel, when below the selected threshold level, are converted to PCM bytes corresponding to the minimum PCM code level before being added to the conference sum. The four threshold levels available correspond to the first, fifth, ninth and sixteenth step of the first segment. These are 1/4096, 9/4096, 16/4096, and 32/4096 with respect to full scale A-Law, and 1/8159, 9/8159, 16/8159, and 32/8159 with respect to full scale -Law (see Table 1). PCM Format Selection PCM digital code assignment is register programmable and achieved through the use of Instruction 5 (see Table 2). The available formats are CCITT G.711 A-Law or -Law, with true-sign Alternate Digit Inversion or true-sign/Inverted Magnitude coding. Output clock Cko provides a reference time base for a digital time/space crosspoint switch. Normally this signal is identical to the master clock input Cki. When operating with the extra bit selection, through Instruction 5, Cko is low for two clock periods, which allows operation of the MT8924 with the 1.544 MHz PCM frame format (see Figure 10). Transparent Mode The MT8924 can operate in transparent mode. In this case the PCM input (DSTi) is passed unmodified through the MT8924 to the output (DSTo) with a delay of one frame and one channel. This feature allows attenuation of specific channels that are not connected to a conference. Tone Insertion The MT8924 provides for tone insertion into PCM output channels by using the two input pins TD and TF. An externally generated square wave tone applied to the TF input will generate a level corresponding to 1/10 of the full scale accumulator value when TD is High. Only channels connected in a conference with the insertion tone bit (IT) active will have the PCM coded tone at their output (see Instruction 1). Testing and Diagnostic Feature
MT8924
For testing and diagnostic purposes, a status instruction has been provided that indicates conference location and attenuation level for each channel requested. This data appears on the databus upon status request.
Programmable Control
Instruction 1 : Conference Mode Connection This function connects a PCM channel to a conference. The control information from the microprocessor consists of two data bytes and one control byte. The first byte contains the conference number (bits D0-D3) and the Start bit S (D4). When S is High, the accumulator registers connected to a conference are initialized. S set to High is only required in Instruction 1 of the first channel connected to a new conference, otherwise S is set LOW to bring other channels into the conference. The second byte contains the number of the channel to be connected (D0-D4), and the Insert Tone Enable bit IT (D5). When IT and TD are both High all the channels belonging to that conference are enabled using the insert tone function. The third byte contains a four bit opcode (D0-D3) plus information about the attenuation level and noise suppression to be applied to the specific channel. Instruction 2 : Transparent Mode Connection This function sets up a PCM channel for transparent mode operation. The control information from the microprocessor consists of one data byte and one control byte. The first byte contains the channel number, and the second byte contains a four bit opcode (D0-D3) and information about attenuation and noise suppression levels to be applied to the specific channel. PCM data on this channel is not added to any conference, but is transferred to the PCM output after a full frame pulse plus one channel delay. It is not affected by the tone control pins (TF, TD). Instruction 3 : Disconnection This function disconnects a PCM channel from a conference. The control information from the microprocessor consists of one data byte and one
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MT8924
control byte. The data byte contains the number of the channel to be disconnected. The second byte contains the opcode (D0-D3). One frame pulse must pass between disconnection and reconnection of the same channel. Instruction 4 : Overflow Status Monitoring This function extracts overflow status information on all existing conferences and transfers it to the microprocessor data bus. This instruction consists of two control bytes which are differentiated by the C/D control signal. C/D set Low reads the status of the first eight conferences, while C/D set High reads the status of the remaining two conferences. A conference is in overflow when the corresponding status bit is high. Instruction 5 : PCM Mode Select This function is used to set the PCM format. The control byte from the microprocessor consists of one data byte. It contains the Extra Bit E (D6), the Format Bits F1-F0 (D5, D4), and the opcode (D0D3). The E bit must be high when the PCM frame contains an extra bit (i.e. 1.544 Mb/s). Normally E is Low. Bits F1-F0 are used to select the PCM byte format, according to Table 2. After RESET the default values correspond to F1 at Low and F0 at High if A-Law is selected, and F1 at High and F0 at High if -Law is selected. All channels must be disconnected when the PCM mode select instruction is sent. They must remain disconnected for at least two frame pulses after the instruction is sent. It is recommended that this instruction be used immediately following a system reset (see RESET pin description).
Preliminary Information
Instruction 6 : Status Monitoring This function is a read operation which consists of a data byte, a control byte, and a status byte. It extracts information for test and diagnostic purposes and transfers it to the microprocessor bus. The first byte contains the channel number, while the second byte contains the opcode (D0D3). The third byte contains the status information about the operating mode of the channel (D4-D7); the attenuation level (D2-D3); and the noise suppression level (D0-D1).
8-8
Preliminary Information
MT8924
Instruction 1 : Channel Connection in Conference Mode
Control Signals CS 0 0 0
S: P3-P0: IT: C4-C0: A1-A0:
Data Bus D7 X X A1 D6 X X A0 D5 X IT T1 D4 S C4 T0 D3 P3 C3 0 D2 P2 C2 1
T1-T0: T1/T0 00 01 10 11
Comments D1 P1 C1 1 D0 P0 C0 1 Conference Number PCM Channel Number and Insertion Tone control Opcode, Attenuation, and Noise Suppression control
RD 1 1 1
C/D 0 0 1
WR 0 0 0
Conference Start Bit Conference Number (1-10) Insertion Tone Function Enable (IT=1) Channel Number (0-31) Channel Attenuation 00 = -0dB 01 = -3dB 10 = -6dB
Channel Noise Suppression A-Law -Law no noise suppression 9/4096 9/8159 16/4096 16/8159 32/4096 32/8159
Instruction 2 : Channel Connection in Transparent Mode
Control Signals CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 X A1 D6 X A0 D5 X T1 Data Bus D4 C4 T0 D3 C3 0 D2 C2 0 D1 C1 1 D0 C0 1 PCM Channel Number Opcode and Attenuation Comments
T1-T0: see noise suppression description given for Instruction 1
Instruction 3 : Channel Disconnection
Control Signals CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 X X D6 X X D5 X X Data Bus D4 C4 X D3 C3 1 D2 C2 1 D1 C1 1 D0 C0 1 PCM Channel Number Opcode Comments
Instruction 4: Overflow Status Monitoring
Control Signals CS 0 0 RD 0 0 C/D 0 1 WR 1 1 D7 CF 8 X D6 CF 7 X D5 CF 6 X Data Bus D4 CF 5 X D3 CF 4 X D2 CF 3 X D1 CF 2 CF 10 D0 CF 1 CF 9 Conferences 1 to 8 Conferences 9 to 10 Comments
CF10 - CF1 : Conference is in overflow when bit is HIGH Note : as long as RD remains LOW, the overflow status of the conference selected by C/D can be monitored in real time
8-9
MT8924
Instruction 5 : PCM Operating Mode Selection
Control Signals CS 0
E: F1 - F0:
Preliminary Information
Data Bus D7 X D6 E D5 F1 D4 F0 D3 0 D2 1 D1 0 D0 1
Comments
RD 1
C/D 1
WR 0
see Table 1
Extra bit insertion (active when E=1) PCM byte format selection (see Table 1) 00 = no bit inverted 01 = even bit (B0, B2, B4, B6) inverted 10 = odd bit (B1, B3, B5) inverted 11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted
Instruction 6 : Status Monitoring
Control Signals CS 0 0 0
P3 - P0:
Data Bus D7 X X P3 D6 X X P2 D5 X X P1 D4 C4 X P0 D3 C3 0 A1 D2 C2 1 A0 D1 C1 1 T1 D0 C0 0 T0
Comments
RD 1 1 0
C/D 0 1 1
WR 0 0 1
Note:
channel mode operation information A1 - A0: see channel attenuation description 0000 = no connection for Instruction 1 1111 = transparent mode T1 - T0: see noise suppression description 1010 - 0001 = conference mode for Instruction 1 P3 - P0 provides conference number Instruction 6 enables the data bus to read the status until reset by C/D=0, WR=1, and CS=0
8-10
Preliminary Information
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Supply Voltage Voltage on any I/O pin Current on any I/O pin Storage Temperature Power Dissipation (plastic package) Symbol VDD - VSS VI/O II/O TST PD - 65 Min - 0.3 VSS - 0.3
MT8924
Max 7 VDD + 0.3 10 + 150 500
Units V V mA C mW
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions
Characteristics 1 2 3 4 Supply Voltage Ambient Operating Temp. Range Input Voltage High Input Voltage Low Sym VDD TOP VIH VIL Min 4.75 0 2.4 VSS Typ* 5 Max 5.25 +70 VDD 0.8 Units V C V V for 400mv noise margin Test Conditions
* Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Characteristics: Clocked operation (TOP=0 to 70C; V DD=5V5%)
Characteristics 1 2 3 4 5 6 7 8 Input Low Level Input High Level Output Low Level Output High Level Output Low Level Input Leakage Current Data Bus Leakage Current Supply Current Sym VIL VIH VOL VOH VOL IIL IOL IDD 2.4 0.4 10 10 10 2.0 0.4 Min Typ Max 0.8 Units V V V V V A A mA Test Conditions Pins 1-3, 6-13, 15-20, 22-23 Pins 1-3, 6-13, 15-20, 22-23 Pins 4, 6-13; IOL=4 mA Pins 4, 6-13; IOL=4 mA Pins 5, 21; IOL=8 mA Pins 1-3, 6-13, 15-20, 22-23; VIN=0 to VDD Pins 6-13; VIN=0 to VDD; CS=VDD Pin 14; Cki=4.096 MHz
All DC characterisitics are valid 250s after VDD and C4i have been applied.
AC Electrical Characteristics - Capacitances
Characteristics 1 2 3 Input Capacitance I/O Capacitance (Bidirectional) Output Capacitance Sym CI CI/O CO Min Typ Max 5 15 10 Units pF pF pF Test Conditions frequency=1MHz; TOP=0 to 70C; unused pins tied to VSS; VDD=5V5%
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MT8924
Preliminary Information
AC Electrical Characteristics - Clocked Timing* (TOP=0 to 70C; V DD=5V5%)
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Clock period Clock low level width Clock high level width Clock rise time Clock fall time Sync. low setup time Sync. low level hold time Sync. high setup time Sync. high width OS propagation delay from rising edge of Clock Cko propagation delay to Clock edges TD setup time TD hold time TD setup time TD hold time Sym tCK tWLCK tWHCK tRCK tFCK tSLSY tHLSY tSHSY tWHSY tPDOS tPDEC tSTD tHTD tSTF tHTD 80 40 80 40 50 40 80 tCK 100 80 Min 230 100 100 25 25 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL=50pF CL=50pF ** Test Conditions
* All AC characteristics are valid 250s after VDD and the clock have been applied. C L is the max. capacitive load and RL is the test pull up resistor. With Extra Bit Insert operating mode these times are 80ns longer. ** With Extra Bit Insert operating mode this time becomes 3tCK.
tCK Cki tWHCK tWLCK tSLSY F0i tHLSY
tRCK
tFCK
tSHSY
tWHSY tSTD TD tSTF TF tPDEC tPDEC tHTF tHTD
Cko tPDOS OS
Figure 5 - Clock Timing
8-12
Preliminary Information
MT8924
AC Electrical Characteristics - PCM Timing* (TOP=0 to 70C; V DD=5V5%)
Characteristics 1 2 3 Input PCM setup time Input PCM hold time Output PCM propagation delay Sym tSPCM tHPCM tPD Min 80 35 25 125 Typ Max Units ns ns ns CL=150pF, RL=1K in 2.048MHz mode ** Test Conditions
*All AC characteristics are valid 250s after VDD and the clock have been applied. CL is the max. capacitive load and R L is the test pull up resistor. **With Extra Bit Insert operating mode these times are 80ns longer.
Cki
0
1
2
F0i tSPCM tHPCM DSTi
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
MSB
tPD DSTo
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
MSB
Figure 6 - PCM Timing
AC Electrical Characteristics - RESET Timing* (TOP=0 to 70C; VDD=5V5%)
Characteristics 1 2 3 4 RESET low setup time RESET low hold time RESET high setup time RESET high level width Sym tSLRES tHLRES tSHRES tWHRES Min 100 50 90 tCK Typ Max Units ns ns ns ns Test Conditions
* All AC characteristics are valid 250s after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up resistor.
Cki tSLRES tHLRES
tSHRES
RESET tWHRES
Figure 7 - Reset Timing
8-13
MT8924
Preliminary Information
AC Electrical Characteristics - Write Timing (TOP=0 to 70C; V DD=5V5%)
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Write Pulse low width Write Pulse high width Repetition Interval between active Write Pulses Read high setup time to active Write Pulse Read high hold time from active Write Pulse Write Pulse rise time Write Pulse fall time CS low setup time to WR falling edge CS low hold time from WR falling edge CS high setup time to WR rising edge Sym tWLWR tWHWR tREPWR tSHRD tHHRD tRWR tFWR tSLCSWR tHLCSWR tSHCSWR tSC/DWR tHCDWR tSDWR tHDWR Min 150 200 500 0 20 60 60 0 0 0 0 130 25 130 25 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Active case Active case Test Conditions
CS high hold time from WR rising edge tHHCSWR C/D setup time to Write Pulse end C/D hold time from Write Pulse end Input setup time to Write Pulse end Input hold time from Bus Write Pulse end
tWLWR WR
tWHWR
tSHRD
tHHRD
tFWR tREPWR
tRWR
RD tSHCSWR CS tHLCSWR tSLCSWR tSCDWR C/D tSDWR DIN tHDWR tHHCSWR tHCDWR
Figure 8 - Write Timing Characteristics
8-14
Preliminary Information
MT8924
AC Electrical Characteristics - Read Timing (TOP=0 to 70C; V DD=5V5%)
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Read Pulse low width Read Pulse high width Repetition Interval between active Read Pulses Write high setup time to active Read Pulse Write high hold time from active Read Pulse Read Pulse rise time Read Pulse fall time Low setup time to RD falling edge Low hold time from RD falling edge High setup time to RD falling edge High hold time from RD rising edge C/D setup time to RD Pulse start Hold time from Read Pulse end Propagation delay from falling edge of Read Pulse Propagation delay from rising edge of Read Pulse to high impedance state Sym tWLRD tWHRD tREPRD tSHWR tHHWR tRRD tFRD tSLCSRD tHLCSRD tSHCSRD tHHCSRD tSCDRD tHCDRD tPDD tHZ 0 0 0 0 20 25 120 80 Min 180 200 500 0 20 60 60 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read; CL=200pF Write; CL=200pF Active case Active case Active case Active case Test Conditions
tWLRD RD
tWHRD
tSHWR
tHHWR
tFRD tREPRD
tRRD
WR tSHCSRD CS tSLCSRD tSCDRD C/D tHZ tHCDRD tHLCSRD tHHCSRD
tPDD DOUT
Figure 9 - Read Timing Characteristics
8-15
MT8924
Extra Bit Cki tPDEC Cko Bit 0 Channel 0
Preliminary Information
Bit 1 Channel 0
F0i
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Figure 10 - CKo Timing with Extra Bit Insertion Mode
Channel N-1 Cki
Channel N
Channel N+1
OS
Figure 11 - OS Timing with Output PCM Channel belonging to a Conference in Overflow
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